This invention relates in general to offset cancellation circuits and, more particularly, to an offset cancellation circuit for reducing pulse pairing.
In computer disk drive applications, an analog signal received from the read/write head as it passes over the disk platter is converted to a digital signal for further processing by the microprocessor. To obtain maximum signal-to-noise ratio for the analog-to-digital conversion, a signal level qualification is performed on the analog signal to ensure its amplitude is sufficient to distinguish over any noise present and to convert it to a digital logic level. Furthermore, it is desirable to generate a clock pulse corresponding to the peak of the analog signal for timing qualification to ensure the corresponding digital signal is sampled at mid-pulse.
Accordingly, the analog signal from the read/write head of the disk drive is typically processed through a differentiator circuit to detect the peak of the analog signal which corresponds to a zero-crossing of the differentiated signal. A comparator circuit changes state at each zero-crossing of the differentiated signal, while a zero-crossing detector is responsive to the output signal of the comparator for generating the clock pulse used to sample the converted digital signal at mid-pulse.
A common problem with the prior art timing qualification circuit is the introduction of a DC offset at the output of the differentiator circuit which has the effect of shifting the zero-crossing point of the differentiated signal and providing inaccurate timing information. The DC offset tends to shift adjacent clock pulse pairs closer together, commonly known as pulse pairing, which causes the digital signal to be sampled off mid-pulse. The clock pulse pairing reduces the margin of identifying in which time window a pulse has occurred. It is desirable to minimize pulse pairing and maintain equal temporal spacing between the clock pulses.
A typical solution for the DC offset problem is to AC-couple the output of the differentiator circuit with capacitors inserted in series to the input of the comparator circuit. The AC-coupled capacitors require values in the range of 0.1 microfarads to effectively remove the DC offset. Such large valued capacitors must be placed external to the integrated circuit (IC) chip, and for differential operation, require four IC pins to connect two external capacitors.
Furthermore, the large value AC-coupled capacitors have an associated long time constant to charge to an operational level. It is common for the differentiator and comparator circuits to be placed in an inoperative sleep mode to conserve power when the disk drive is not being accessed. Yet, the timing qualification circuit must begin operating very rapidly once a disk read request is issued. The large value capacitors tend to limit the operating speed of the disk drive by nature of the charge time for the external capacitors when returning to operation from sleep mode.
Hence, what is needed is an improved offset cancellation circuit for removing DC offset while reducing pin allocation for external capacitors and reducing the circuit start-up time after periods of non-operation.